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NT6827 i 2 c bus controlled on-screen display 1 v2.0 features n i 2 c bus interface with slave address $7a (transmitter) & $7b (receiver) n horizontal frequency range: 30khz ~ 120khz n flexible display resolution up to 1524 dots/row n internal pll generates a stable and wide-range system clock (96mhz) n osd screen consists of character array of 15 rows by 30 columns n programmable vertical and horizontal positions for osd display center n total of 272 rom fonts including 256 standard & 16 multi-color rom fonts. n 12 x 18 dot matrix per character n 8-color selection for each character n 7-color selection for each character background n character/symbol blinking, shadowing & bordering display effect n double character height and width for each row n programmable height for character/symbol displaying n row to row spacing control to avoid expansion distortion n four programmable windows with overlapping capability and shadowing effect n color setting for windows ? background and characters ? shadowing & bordering n fade-in/out effect of osd screen display n selectable hsync & vsync input polarity general description NT6827 is designed for displaying symbols and characters onto a crt monitor. its operation is controlled by a micro- controller with an i 2 c bus interface. by sending proper data and commands to NT6827, it can carry out the full screen display automatically with the time base being generated by an on-chip pll circuit. there are many functions provided by this chip to fully support the user applications, such as: adjustment of the osd windows position, built-in 256 rom & 16 multi-color fonts, variable character height with row-to-row spacing adjustment, 8 color selections & 7 background color controls for each character, double height/width controls for each row, 4 overlapping windows available with color & size controls, size controls for each window shadowing, color selection for windows ? shadowing & characters ? shadowing/ bordering and fade-in/out display effect ,etc.
NT6827 2 block diagram i 2 c bus receiver scl sda vsync vflb hsync hflb vpol hpol display memory contol reg. rom font 12 * 18 output control r/g/b fbkg pwm / hfton power system avcc power on low voltage reset timing generator dvcc agnd dgnd vertical control pll circuit rp vco horizontal control bus control buffer display effect color control test circuit
NT6827 3 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 16 15 14 13 agnd vco rp avcc hflb n.c. sda scl dgnd r g b fbkg pwm / hfton vflb dvcc NT6827
NT6827 4 pin description NT6827 name i/o/p/r function 1 agnd p analog ground 2 vco - voltage i/p to control oscillator 3 rp - bias resistor. it is used to bias internal vco to resonate at the specific dot frequency. 4 avcc p analog power supply (5v typ) 5 hflb i horizontal fly-back input ( schmitt trigger buffer) 6 n.c. - - 7 sda i sda pin of i 2 c bus ( schmitt trigger buffer) with internal 100k ohm pulled-high resistance 8 scl i scl pin of i 2 c bus ( schmitt trigger buffer) with internal 100k ohm pulled-high resistance 9 dvcc p digital power supply (5v typ) 10 vflb i vertical fly-back input ( schmitt trigger buffer) 11 pwm/ hfton o pwm output or gain controller of r, g, b channels. 12 fbkg o fast blanking output. it is used to cut off the external r, g, b signals. 13 b o blue color output with push-pull output structure 14 g o green color output with push-pull output structure 15 r o red color output with push-pull output structure 16 dgnd p digital ground
NT6827 5 dc/ac absolute maximum ratings* recommended operation conditions vcc (measured to gnd) . . . . . . . . . . . . 4. 7 5v to 5. 2 5v operating temperature . . . . . . . . . . . . . . 0 to +70 0 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these, or under any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (vdd = 5v, tamb = 25 c) symbol parameter min. typ. max. unit notes vcc supply voltage 4. 7 5 5 5. 2 5 v - dc characteristic symbol parameter min. typ. max. unit notes i dd operating current - 22 25 ma no loading vih1 input high voltage 2 - - v vflb, hflb with schmitt trigger buffer vil1 input low voltage - - 0.8 v vflb, hflb schmitt trigger buffer vih2 iic bus input high voltage 3 - - v vil2 iic bus input low voltage - - 1.5 v scl, sda idrive1 driving current of r, g, b, fbkg, hfton output pins at 2.4v output voltage 80 - - ma - isink1 sinking current of r, g, b, fbkg, hfton output pins at 0.4v output voltage 20 - - ma - ileak leakage current of r, g, b, fbkg pins at hi-z state - - 10 ua measured at 2.5v state iiicl iic bus output sink current - 5 - ma viicoutl = 0.4v vth input threshold voltage at hflb & vflb pin 1.8 2.0 2.2 v - vstih schmitt trigger input high voltage 1.7 2 v - vstil schmitt trigger input low voltage 0.8 1.1 - v - iin input current of hsync, vsync, sda, scl pins -10 - +10 ua schmitt trigger buffer
NT6827 6 1.1v 1.7v vh vl output state input voltage figure 1. schmitt trigger diagram ac characteristic symbol parameter min. typ. max. unit notes fhfy horizontal fly-back frequency 30 - 120 khz - - - 5 v - vhfly horizontal fly-back input 0 - - v - thflymin minimum pulse width of horizontal fly-back 0.7 - - us - thflymax maximum pulse width of horizontal fly-back - - 5.5 us - fvfy vertical fly-back frequency 50 - 200 hz - - - 5 v - vvfly vertical fly-back input 0 - - v - tvflymin minimum pulse width of vertical fly-back 20 - - us - tvflymax maximum pulse width of vertical fly-back - - 1 ms - hflb 2.0 v thwidth 0 v 5 v vflb 2.0 v tvwidth 0 v 5 v figure 2. h/v fly-back signal
NT6827 7 i 2 c bus ? slave transmitter & receiver (slave address: $7a & $7b) table 1. i 2 c bus symbol parameter min. typ. max. unit notes fmaxcl maximum scl clock frequency 100 khz vil input low voltage -0.5 1.5 v vih input high voltage 3.0 5.5 v tlow low period of the scl clock 4.7 us thigh high period of the scl clock 4.0 us tsudat data setup time 250 ns thddat data hold time 300 ns tiicr rising time of iic bus 1000 ns tiicf falling time of iic bus 300 ns tsusta setup time for repeated start condition 1.3 us thdsta hold time for start condition 4.0 us tsusta setup time for start condition 4.7 us tsusto setup time for stop condition 4.0 us scl, sda tiicbuf time the iic bus must be free before the next new transmission can start 4.7 us iiicl iic bus sink current 4 5 ma viicoutl = 0.4 v tfilter input filter spike suppression 100 ns scl, sda scl sda tiicbuf thdsta tsudat thigh tiicr tiicf thddat tlow stop start tsusta thdsta stop tsusto start figure 3. i 2 c bus timing
NT6827 8 memory map 29 14 0 7 0 7 row attribute register row attribute register row 7 0 30 column 0 0 0 display register fonts address $00-$ff 7 figure 4. memory map of display register (row 0 - 14) 0 29 14 0 0 7 0 7 column row character attribute register character attribute register figure 5. memory map of attribute register (row 0 - 14)
NT6827 9 row 0 15 0 7 0 7 window 1-4 control register column 11 window1 - window4 osd screen control 12 22 0 7 0 7 osd screen control register 23 0 7 reset flag control register figure 6. memory map of control register (row 15)
NT6827 10 list of control registers: (1) display register: row 0 - 14, column 0 - 29 7 6 5 4 3 2 1 0 row 0 - 14 column 0 - 29 msb lsb font ? s address $00 - $ff bit 7 - 0: these eight bits address one of the 256 characters/symbols residing in the character rom fonts. note that if the user clear the mcfont bit (row 15, column 20) to ? 0 ? , the 0 ~ 255 will address the standard rom fonts, and if sets this bit to "1", the 0 ~ 239 will address the standard rom fonts & the 240 ~ 255 will address the multi-color rom fonts. (2) character attribute register: row 0 - 14, column 0 - 29 7 6 5 4 3 2 1 0 row 0 - 14 column 0 - 29 bkr bkg bkb blnk r g b character ? s attribute control bit 6 - 4: bkr/g/b- these three bits define the color attributes of the background for the corresponding haracter/symbol. if all three bits are cleared, no background will be displayed. refer to the table 8 for the color selections. bit 3: blnk - this bit enables the blinking effect of the corresponding character/symbol when set to ? 1 ? . the blinking frequency is approximately 1hz with a fifty-fifty duty cycle at 80hz vertical sync frequency. bit 2 - 0: r/g/b -these three bits define the color attributes of the corresponding character/symbol. refer to the table 7 for the color selections. table 7. character/windows color selection color r g b black 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 table 8. character/windows ? background color selection color r g b no background 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1
NT6827 11 ( 3) row attribute register: row 0 - 14, column 30 7 6 5 4 3 2 1 0 row 0 - 14 column 30 dbh dbw row ? s attribute control bit 1: dbh- this bit controls the height of the displayed character/symbol. when this bit is set, the character/symbol is displayed in double height. bit 0: dbw- this bit controls the width of the displayed character/symbol. when this bit is set, the character/symbol is displayed in double width. (4) window 1 registers: row 15, column 0 7 6 5 4 3 2 1 0 row start address row end address row 15 column 0 msb lsb msb lsb window 1 row size control bit 7 - 4: these bits determine the row start position of window 1on the 15*30 osd screen. bit 3 - 0: these bits determine the row end position of window 1on the 15*30 osd screen. 7 6 5 4 3 2 1 0 column start address row 15 column 1 msb lsb winen shad window1 column size control & attribute control bit 7-3: these bits determine the column start position of window 1on the 15*30 osd screen. bit 2: winen - this bit enables window 1 when it is set. the default value of it is '0' after power on. bit 0: shad - this bit enables the shadowing on the window when it is set to ? 1 ? . the default value of it is '0' after power on. 7 6 5 4 3 2 1 0 column end address row 15 column 2 msb lsb r g b window1 column size control & attribute control bit 7 - 3: these bits determine the column end position of window 1on the 15*30 osd screen. bit 2 - 0: r/g/b - these bits control the background color of window 1. refer to table 7 for color selection. note: window 1 control registers occupy column 0 - 2 of row 15, window 2 from column 3 - 5, window 3 from 6 - 8 and window 4 from 9 - 11. the function of window 2 - 4 control registers is the same as window 1. window 1 has the highest priority, and window 4 the least. the higher priority color will take over on the overlapped window area. if the start address of the row/column is greater than the end address, this window will not be displayed. an out of range setting (over the 15 row or 30 column range) will cause abnormal operation.
NT6827 12 (5) osd screen position control registers: row 15, column 12 - 13 7 6 5 4 3 2 1 0 vpos row 15 column 12 msb lsb vertical position adjustment bit 7 - 0: vpos - these bits determine the vertical starting position for the character display. it is the vertical delay starting from the leading edge of vflb. the unit of this setting is 4 horizontal lines and the equation is defined as below: vertical delay = ( vpos * 4 +1) * horizontal line the default value of it is 4 ($04) after power on. 7 6 5 4 3 2 1 0 hpos row 15 column 13 msb lsb horizontal position adjustment bit 7 - 0 : hpos - these bits determine the horizontal starting position for the character display. it is the horizontal delay starting from the leading edge of hflb. the unit of this setting is 6 dots movement shift to right on the monitor screen and the equation is defined as below: horizontal delay = ( hpos * 6 + 49) / p.r. where the p.r. (pixel rate ) is defined by the hdr & horizontal frequency. p.r. (pixel rate) = hdr * 12 * freq hflb refer to the hdr control register at row15 / column15 for the p.r. setting. the default value of these bit is 15 ($ 0f) after power on.
NT6827 13 (6) character height control: row 15, column 14 7 6 5 4 3 2 1 0 row 15 column 14 crh6 crh5 crh4 crh3 crh2 crh1 crh0 character ? s height control bit 6 - 0: crh6 - crh0 - these bits determine the displayed character height. the character, with an original 12 by 18 font matrix, can be expanded from 18 to 71 lines. refer to the table 9 below. all of these bits will be cleared to ? 0 ? after power on. if the setting value of ch0 - ch6 is great than 17, then the algorithm will repeat at most 17 lines. table 9. lines expanded control crh6 ~ crh0 lines inserted crh6 = ? 1 ? , crh5 = ? 1 ? all 18 lines repeat twice crh6 = ? 1 ? , crh5 = ? 0 ? all 18 lines repeat once crh6 = ? 0 ? , crh5 = ? x ? repeat at most 17 lines crh4 = ? 1 ? insert 16 lines crh3 = ? 1 ? insert 8 lines crh2 = ? 1 ? insert 4 lines crh1 = ? 1 ? insert 2 lines crh0 = ? 1 ? insert 1 line table 10. lines expanded position repeat position no. of lines inserted 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 insert 1 line ! insert 2 lines ! ! insert 4 lines ! ! ! ! insert 8 lines ! ! ! ! ! ! ! ! insert 16 lines ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! insert 17 lines ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
NT6827 14 (7) flexible display control register: row 15, column 15 7 6 5 4 3 2 1 0 hdr row 15 column 15 msb lsb horizontal display resolution control bit 6 - 0: hdr - these bits determine the resolution of the horizontal display line. the unit of this setting is twelve dots (one character). with a total of 92 steps ($24 ~ $7f: 36 ~ 127 steps. its value can ? t be smaller than 36 at anytime), the user can adjust the resolution from 36 to 127 characters on each horizontal line. note that the resolution adjustment must be done in cooperation with the vco setting at the row15/column18 control register. refer to the table 11 of the control register at row15/column18. the default value of it is 40 after power on. (8) osd row to row space control register: row 15, column 16 7 6 5 4 3 2 1 0 r2rspace row 15 column 16 msb lsb row to row space adjustment bit 4 - 0: r2rspace - these bits define the row to row spacing in the units of horizontal line. it means extra lines, defined by this 5-bit value, will be appended to each display row. the default value of it is '0' after power on and there are no extra lines inserted between the rows. all of these bits will be cleared to ? 0 ? after power on. (9) input/output control register: row 15, column 17 7 6 5 4 3 2 1 0 row 15 column 17 osden bsen shadow fade blank clrwin clrdspr fbkgc osd screen control 1 bit 7: osden - this bit will enable the osd circuit when it is set to ? 1 ? . the default value is ? 0 ? after power on. bit 6: bsen - this bit will enable the bordering and shadowing effect when it is set to ? 1 ? . the default value is ? 0 ? after power on. bit 5: shadow - when the bsen is set to ? 1 ? , it will enable the shadowing effect when this bit set to ? 1 ? , too. otherwise, it will enable the bordering effect when this bit is cleared to ? 0 ? . the default value is ? 0 ? after power on. bit 4: fade - this bit enables the fade-in/out effect when the osd screen is turned on by changing osden from ? 0 ? to ? 1 ? or when turned off by changing osden from ? 1 ? to ? 0 ? . the fade-in/out effect will be completed in about 0.5 seconds when the input vsync is 60 hz. the default value of this bit is ? 0 ? after power on . bit 3: blank - this bit will force the fbkg pin to output high when this bit & the fbkgop bit is set to ? 1 ? . otherwise, the fbkg pin will output low when this bit is set to ? 1 ? & the fbkgop bit is set to ? 0 ? . the default value of this bit is ? 0 ? after power on . bit 2: clrwin - this bit will clear all windows ? winen control bit when it is set to ? 1 ? . the default value of this bit is ? 0 ? after power on . bit 1: clrdspr - this bit will clear all of the contents in the display registers and the r, g, g, blnk bit s in the character attribute registers when it is set to ? 1 ? . the default value of this bit is ? 0 ? after power on . bit 0: fbkgc - it determines the configuration of the fbkg output pin. when it is cleared, the fbkg pin will output high when displaying characters or windows. otherwise, it will output high only when displaying characters. the default value of this bit is ? 0 ? after power on.
NT6827 15 7 6 5 4 3 2 1 0 row 15 column 18 rgbf fbkgop pwmctrl dbounce hpol vpol vco1 vco0 osd screen control 2 bit 7: rgbf - this bit controls the driving state of the output pins, r, g, b and fbkg when the osd is disabled. after power on, this bit is cleared to ? 0 ? and all of the r, g, b and fbkg pins output high impedance state while the osd is being disabled. if this bit is set to ? 1 ? , the r, g, b output pins will drive low and the fbkg pin will drive high or low depending on the fbkgop (if fbkgop=0, it will drive high. if fbkgop=1, it will drive low) while the osd is being disabled. bit 6: fbkgop - this bit selects the polarity of the output signal of the fbkg pin. this signal is active low when the user clears this bit. otherwise, active high, set this bits. refer the figure 7 below for the fbkg output timing. the default value is ? 1 ? after power on. bit 5: pwmctrl - this bit selects the output option to the pwm/hfton pin. this bit will enable the pwm output when it is set to ? 1 ? . otherwise, it will select the hfton option. refer to the figure 7 below for the hfton output timing. the default value is ? 0 ? after power on. bit 4: dbounce - this bit is to activate the debounce circuit of the horizontal and vertical scan. it is to prevent the osd screen shaking when the user adjusts the horizontal phase or vertical position. this bit will be cleared after power on. bit 3: hpol - this bit selects the polarity of the input signal of the horizontal sync (hflb pin). if the input sync signal has negative polarity, the user must clear this bit. otherwise, set this bit to ? 1 ? to accept the positive polarity signal. after power on, this bit is cleared to ? 0 ? and it will accept a negative polarity sync signal. bit 2: vpol - this bit selects the polarity of the input signal of the vertical sync (vflb pin). if the input sync signal has negative polarity, the user must clear this bit. otherwise, set this bit to ? 1 ? to accept the positive polarity signal. after power on, this bit is cleared to ? 0 ? and it will accept a negative polarity sync signal. bit 1 - 0: vco1/0 ? these bits select the vco frequency range when the user sets the horizontal display resolution flexibly. it is related to the horizontal display resolution and the user must set the control register at row15/column15 properly. the default value is vco1 = 0 & vco0 = 0 after power on state. the relationship between vco1/0 and the display resolution is list below: table 11. p.r . (pixel rate) = hdr * 12 * freq hflb section vco1 vco0 vco freq. min vco freq. max unit p.r. limit hflb freq. limit freq1 0 0 6 12 freq2 0 1 12 24 freq3 1 0 24 48 freq4 1 1 48 92.2 mhz min < p.r. < max ( min/hdr*12 ) < freq hflb < max/( hdr*12 ) if there is no signal at hflb input, the pll will generate an approximate 2.5 mhz clock to ensure the proper operation of i 2 c bus and other control registers.
NT6827 16 window background window background chacracter background chacracter background chacracter shadowing fbkgop bit = ? 1 ? fbkgc bit = ? 1 ? fbkg hfton fbkgop bit = ? 1 ? fbkgc bit = ? 0 ? figure 7. fgbk & hfton output timing
NT6827 17 (10) color selection for shadowing/bordering effect: row 15, column 19 7 6 5 4 3 2 1 0 row 15 column 19 winr wing winb chr chg chb shadowing/bordering color control bit 6 - 4: winr/g/b - these bits control the shadowing color of windows 1-4. refer to the table 12 for color selection. all of these bits will be cleared to ? 0 ? after power on. bit 2 - 0: chr/g/b - these bits control the shadowing/bordering color of each character. refer to the table 12 for color selection. all of these bits will be cleared to ? 0 ? after power on. table 12. character/windows ? shadowing color selection color r g b black 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 (11) multi-color fonts ? control: row 15, column 20 7 6 5 4 3 2 1 0 row 15 column 20 mcfont multi-color fonts control bit 0: mcfont - this bit will enable the multi-color fonts addressed from 240 to 255 when it is set to ? 1 ? . the default value is ? 0 ? after power on and enables the standard rom fonts.
NT6827 18 (12) adjustments of width & height for windows ? shadowing: row 15, column 21, 22 7 6 5 4 3 2 1 0 row 15 column 21 w4wd1 w4wd0 w3wd1 w3wd0 w2wd1 w2wd0 w1wd1 w1wd0 setting of windows ? shadowing width wxwd1/0 - these bits will determine the size of the window ? s width when the shad bit of the windows control register (row 15 column 1, 4, 7, 10) is set to ? 1 ? . the default values are ? 0, 0 ? after power on. refer to the table 13 below for the size adjustments. table 13. windows ? shadowing width control wxwd1/0 ( 0 , 0 ) ( 0 , 1 ) ( 1 , 0 ) ( 1 , 1 ) units windows ? shadowing width 2 4 6 8 pixels 7 6 5 4 3 2 1 0 row 15 column 22 w4ht1 w4ht0 w3ht1 w3ht0 w2ht1 w2ht0 w1ht1 w1ht0 setting of windows ? shadowing height wxht1/0 - these bits will determine the size of the window ? s height when the shad bit of the windows control register (row 15 column 1, 4, 7, 10) is set to ? 1 ? . the default values are ? 0 ? after power on. refer to the table 14 below for the size adjustments. table 14. windows ? shadowing height control wxht1/0 ( 0 , 0 ) ( 0 , 1 ) ( 1 , 0 ) ( 1 , 1 ) units windows ? shadowing height 2 4 6 8 pixels (13) reset flag control registers 7 6 5 4 3 2 1 0 row 15 column 23 resetflg bit 1: restflg - after system reset, the system will clear this bit. the user can set this bit at the beginning t o check if this bit has been cleared by the system reset action . this bit can be read back through the iic bus by an external master device, for example, an mcu. the other bits are reserved.
NT6827 19 (14) reserved control register: 7 6 5 4 3 2 1 0 row 15 column 24 reserved this control register is reserved and no data can be written into this register. 7 6 5 4 3 2 1 0 row 15 column 31 reserved this control register is reserved and no data can be written into this register. iic bus read mode operation ?g type (1) (2) (3) (16) (a) start condition osd slave address ? $7b ? row15 column 23 data stop condition 8 bits 8 bits the user may read these bytes of data sequentially and check the reset flag on row 15 column 23 . every time the user sends the start condition and slave address $7b, the nt682 7 will respond with an acknowledge ment and then transmit the data . it is prohibited to read extra data more than 1 bytes of data.
NT6827 20 i 2 c bus communication : f igure 8 shows the i 2 c bus transmission format. the master initiates a transmission routine by generating a start condition, followed by a slave address byte. once the address is properly identified, the slave will respond with an acknowledgement (ack) signal by pulling the sda line low during the ninth scl clock. each data byte which then follows must be eight bits long, plus the ack bit, to make up nine bits together. this ack bit is sent by NT6827 during write mode operation and by the master, during read mode. in write mode, appropriate row and column address information and display data can be downloaded sequentially from the master in one of the three transmission formats, described in figure 8 access register operation. in read mode, the content in some control registers can be transferred to the master. in the cases of no ack or completion of the data transfer, the master will generate a stop condition to terminate the transmission routine. note that the osd_en bit must be set after all the display information has been sent in order to activate the displaying circuitry of NT6827, so that the received information can then be displayed. write operation of the control registers : after the proper identification by the receiving device, a data train of arbitrary length is transmitted from the master. there are three transmission formats from (a) to (c) as stated below timing. the data train in each sequence consists of a row address, a column address and data. in format (a), data must be preceded by the corresponding row address and column address. this format is particularly suitable for updating small amounts of data between different rows. however, if the current information byte has the same row address as the one before, format (b) is recommended. for a full screen pattern change which requires a massive information update, or during a power up situation, most of the row and column addresses in either (a) or (b) format will appear to be redundant. a more efficient data transmission format (c) should be applied. this sends the starting row and column addresses once only, and then treats all subsequent data as display information. the row and column addresses will be automatically incremented internally for each display information data from the starting location. to differentiate the row and column addresses when transferring data from the master, the msb (most significant bit) is set as table 15 transmission: ? 1 ? represents the row, with ? 0 ? representing the column address. furthermore, to distinguish the column address in formats (a), (b) and (c), the sixth bit of the column address is set to ? 1 ? , which represents format (c), and to ? 0 ? for format (a) or (b). there is some limitation on using mixed formats during a single transmission. it is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b).
NT6827 21 i 2 c bus write operation timing : 3 --------------- repeat -------------- 4 type (1) (2) (3) (4) (5) (3) (4) (5) (6) (a) start condition osd slave address ? $7a ? row address data column address data information data row address data column address data information data ? stop condition 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 3 ------ repeat ----- 4 type (1) (2) (3) (4) (5) (4) (5) (6) (b) start condition osd slave address ? $7a ? row address data column address data information data column address data information data ? stop condition 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 3 repeat 4 type (1) (2) (3) (4) (5) (5) (5) (6) (c) start condition osd slave address ? $7a ? row address data column address data information data information data information data ? stop condition 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits figure 8. access register read operation table 15. address data transmission for registers item no address b7 b6 b5 b4 b3 b2 b1 b0 type 1 row 1 0 0 x d d d d (a),(b),(c) 2 column 0 0 x d d d d d (a),(b) display register 3 column 0 1 x d d d d d (c) 4 row 1 0 1 x d d d d (a),(b),(c) 5 column 0 0 x d d d d d (a),(b) attribute / control register 6 column 0 1 x d d d d d (c)
NT6827 22 read operation of the control registers : not all of the control registers can be read by the master via iic bus of the read mode. below is listed the proper identification of the slave address ($7b) by the nt682 7 , one byte of data is transmitted to the master. the u ser only check s bit1 of this byte transmission data. ( the reset flag on row 15 column 23), item register bytes 1 row 15 column 23 control register 1 i 2 c bus read operation timing : type (1) (2) (3) ( 4 ) (a) start condition osd slave address ? $7b ? row15 column 23 data stop condition 8 bits 8 bits figure 9: access register write operation the user may read these bytes of data and check the reset flag on row 15 column 23 . every time the user sends the start condition and the slave address $7b, the nt682 7 will respond with an acknowledgement and then transmit data . it is prohibited to read extra data more than 1 bytes of data.
NT6827 23 font access ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0 a ) ( 0 b ) ( 0 c ) ( 0 d ) ( 0 e ) ( 0 f ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1 a ) ( 1 b ) ( 1 c ) ( 1 d ) ( 1 e ) ( 1 f ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ( 29 ) ( 2 a ) ( 2 b ) ( 2 c ) ( 2 d ) ( 2 e ) ( 2 f ) ( d0 ) ( d1 ) ( d2 ) ( d3 ) ( d4 ) ( d5 ) ( d6 ) ( d7 ) ( d8 ) ( d9 ) ( da ) ( db ) ( dc ) ( dd ) ( de ) ( df ) ( e0 ) ( e1 ) ( e2 ) ( e3 ) ( e4 ) ( e5 ) ( e6 ) ( e7 ) ( e8 ) ( e9 ) ( ea ) ( eb ) ( ec ) ( ed ) ( ee ) ( ef ) ( f0 ) ( f1 ) ( f2 ) ( f3 ) ( f4 ) ( f5 ) ( f6 ) ( f7 ) ( f8 ) ( f9 ) ( fa ) ( fb ) ( fc ) ( fd ) ( fe ) ( ff ) . . . rom fonts figure 10. 256 standard rom font configuration ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0 a ) ( 0 b ) ( 0 c ) ( 0 d ) ( 0 e ) ( 0 f ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1 a ) ( 1 b ) ( 1 c ) ( 1 d ) ( 1 e ) ( 1 f ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ( 29 ) ( 2 a ) ( 2 b ) ( 2 c ) ( 2 d ) ( 2 e ) ( 2 f ) ( d0 ) ( d1 ) ( d2 ) ( d3 ) ( d4 ) ( d5 ) ( d6 ) ( d7 ) ( d8 ) ( d9 ) ( da ) ( db ) ( dc ) ( dd ) ( de ) ( df ) ( e0 ) ( e1 ) ( e2 ) ( e3 ) ( e4 ) ( e5 ) ( e6 ) ( e7 ) ( e8 ) ( e9 ) ( ea ) ( eb ) ( ec ) ( ed ) ( ee ) ( ef ) ( f0 ) ( f1 ) ( f2 ) ( f3 ) ( f4 ) ( f5 ) ( f6 ) ( f7 ) ( f8 ) ( f9 ) ( fa ) ( fb ) ( fc ) ( fd ) ( fe ) ( ff ) . . . rom fonts multi-color rom fonts figure 11. 240 standard rom font configuration & 16 multi-color rom font
NT6827 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 figure 12. 12 x 18 dots font 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 figure 13. bordering effect figure 14. shadowing effect
NT6827 25 osd screen position : figure, below, illustrates the positions of all display characters on the screen relative to the leading edge of the horizontal and vertical fly-back signals. u raster hflb vflb osd screen 15 30 ( 30*12 =360 dots ) hpos *6 + 49 dots vpos *4 + 1 lines vflb hflb t t figure 15. osd screen position
NT6827 26 osd display format : osd screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 double height double width 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 line expanded = 22 lines & double width line expanded = 22 lines & double height figure 16. osd display format
NT6827 27 osd window setting : column start address row end address row start address 15 30 window1/2/3/4 area row start/end control register: row15 /column 0/3/6/9 column start control register: row15 /column 1/4/7/10 column end control register: row15 /column 2/5/8/11 window color control register: row15 /column 2/5/8/11 column end address figure 17. windows ? size setting window area width height height width width adjustment control register : row15 /column 21 height adjustment control register : row15 /column 22 shadow colorselection control register : row15 /column 19 note : width adjustment units : pixels height adjustment units : h lines osd screen area ( 15 row by 30 column ) figure 18. windows ? shadowing setting
NT6827 28 characters ? programmable height : table 16. line expanded example 1: if user sets crh0 = 1, crh2 = 1, crh3 = 1 line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 original font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! crh0 ! crh2 ! ! ! ! crh3 ! ! ! ! ! ! ! ! ch4 ? ch 0 <= 18 ! ! ! ! ! ! ! ! ! ! ! ! ! result : 31 lines 18+ 8*crh3+4*crh2 +crh0 ! !! !! !! ! !! !! !! !! !! !! !! ! !! !! !! ! ! example 2: if user sets crh0 = 1, crh 3 = 1, crh4 = 1 line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 original font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! crh0 ! crh3 ! ! ! ! ! ! ! ! crh4 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ch4 ? ch 0 >= 18 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! result : 35 lines 18+17 !! !! !! !! !! !! !! !! !! !! !! !! !! !! !! !! !! ! example 3: if user sets crh1 = 1, crh3 = 1, ch5 = 0, ch6 = 1 line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 original font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! crh1 ! ! crh3 ! ! ! ! ! ! ! ! ch4 ? ch0 < 18 ! ! ! ! ! ! ! ! ! ! crh6,5=(1,0) ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! result : 46 lines 18+( 8 * crh3 ) + (2*crh1)+ 18 * 1 !! !!! !! !!! !!! !!! !! !!! !! !!! !! !!! !!! !!! !! !!! !! !!
NT6827 29 multi-color font operation : multi-color font r g b o/p green cyan red figure 19. multi-color font operation in the example above, the novatek logo consists of four fonts. the r, g, b output channels will send out their corresponding font data and it can then display multiple colors in the same font. reminder: when using the multi-color font, it can not be set to black color and the bordering and shadowing options are not available.
NT6827 30 fi gure 20. font code example NT6827 - 00012
NT6827 31 fi gure 21. font code example NT6827-00012 (multi color fonts)
NT6827 32 fi gure 22. font code example NT6827-00013 fi gure 23. font code example NT6827-00013 (multi color fonts)
NT6827 33 application circuit 100 100 100 470 100p 100p 470 100p 220 100 100p 1m 5.6k 0.01uf 12k 470 100p 470 0.1u 5.6k 0.1u 220u 0.01uf 100p 220u u? NT6827 dgnd 16 agnd 1 r 15 g 14 vco 2 b 13 rp 3 fbkg 12 pwm/hfton 11 avcc 4 vflb 10 hflb 5 dvcc 9 n.c 6 sda 7 scl 8 vcc hflb sda scl rout bout fbkg hfton vflb vcc gout
NT6827 34 package information p-dip 16l outline dimensions unit: inches/mm 1 8 16 d e 1 s a 2 a l c e e a \ 9 b 1 b e 1 base plane a 1 seating plane symbol dimension in inch dimension in mm a 0.175 max. 4.45 max. a 1 0.010 min. 0.25 min. a 2 0.1300.010 3.300.25 b 0.018 +0.004 0.46 +0.10 -0.002 -0.05 b 1 0.060 +0.004 1.52 +0.10 -0.002 -0.05 c 0.010 +0.004 0.25 +0.10 -0.002 -0.05 d 0.750 typ. (0.770 max.) 19.05 typ. (19.56 max.) e 0.3000.010 7.620.25 e 1 0.250 typ. (0.262 max.) 6.35 typ. (6.65 max.) e 1 0.1000.010 2.540.25 l 0.1300.010 3.300.25 \ 0~ 15 0~ 15 e a 0.3450.035 8.760.89 s 0.040 max. 1.02 max. note: 1. the maximum value of dimension d includes end flash. 2. dimension e1 does not include resin fins. 3. dimension s includes end flash.

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